1. Field of the Invention
The invention relates to a radiation-hardened memory storage unit that is resistant to total ionizing dose effects.
2. Description of the Related Art
In aerospace electronic systems, the memory is a very important part occupying most of the chip area. In the space environment, an electronic system suffers radiations from the Galaxy, the Sun, the Earth and other radiators. Therefore, the memory is one of the most vulnerable parts in an aerospace electronic system for its high density.
The total ionizing dose radiation is one of the most important radiation effects suffered by the memory. In the 0.18 um process and advanced processes, as the gate oxide thickness is less than 5 nm, the threshold drift of a MOS transistor caused by the total ionizing dose radiation suffered by the gate oxide is negligible, and the leakage current caused by the total ionizing dose radiation suffered by the field oxide in an NMOS transistor is the main effect.
A conventional memory storage unit is shown in FIG. 1 which illustrates a static random access memory (SRAM) containing six transistors. A PMOS transistor 101 and a PMOS transistor 102 are pull-up transistors, an NMOS transistor 103 and an NMOS transistor 104 are pull-down transistors, and an NMOS transistor 105 and an NMOS transistor 106 are access transistors. The PMOS transistor 101 and the NMOS transistor 103 form an inverter, the PMOS transistor 102 and the NMOS transistor 104 form another inverter, and the two inverters are cross-coupled to lock the storage levels of a storage node Q1 and a storage node QN1. Access to the memory storage unit in FIG. 1 is controlled by a word line 107. Specifically, when the word line 107 is high level, data are written into the storage nodes Q1 and QN1 through a bit line 108 and a bit line 109, or data are read out from the storage nodes Q1 and QN1 through the bit lines 108 and 109.
The memory storage unit shown in FIG. 1 is mainly realized by total ionizing dose radiation hardening via the NMOS transistors with the particular gate shapes in FIG. 2 and FIG. 3. An NMOS transistor is hardened by an annular FET layout in FIG. 2. Specifically, one of a drain 202 and a source 203 is completely surrounded by a gate 201 so as to cut off the channel of the leakage current physically to realize total ionizing dose radiation hardening. An NMOS transistor is hardened by a horseshoe FET layout in FIG. 3. Specifically, one of a drain 302 and a source 303 is semi-surrounded by a gate 301 so as to extend the channel length of the leakage current to reduce the leakage current caused by the total ionizing dose radiation to realize total ionizing dose radiation hardening.
However, methods for hardening total ionizing dose radiation in FIG. 2 and FIG. 3 may result in a substantial increase in storage unit area.